3. Bus Interfaces in ARM Cortex-M4
1. STM32F4 Buses Explained
Reference: RM0390 Reference Manual, Section 2.1.
Instruction Code Bus (I-Code)
I-Code bus links the instruction bus in the Cortex-M4 (with its FPU core) to the BusMatrix. Its primary function is to fetch instructions for the core. It targets memory regions that contain executable code, whether that's internal Flash memory, SRAM, or external memory via the FMC.
Data Code Bus (D-Code)
The D-Code bus is another link between the Cortex-M4 FPU core and the BusMatrix, but this one's focused on data. It's used for operations like literal load and debug access. This bus can target memory containing either code or data, again using either internal Flash or external memory via the FMC.
System Bus (S-Bus)
The S-Bus is more versatile and connects the Cortex-M4 FPU core's system bus to the BusMatrix. This bus is typically used for accessing peripheral data or data in SRAM. While it can fetch instructions, doing so is less efficient than using the I-Code bus. It can access a variety of targets including internal SRAMs, various AHB and APB peripherals, and external memories via FMC and QUADSPI.
DMA Memory Bus
This bus is specially designed to handle Direct Memory Access (DMA). It connects the DMA master interface to the BusMatrix and facilitates data transfers between different types of memory like internal Flash, SRAM1, SRAM2, and external memories via FMC and QUADSPI.
DMA Peripheral Bus
This bus, also tied to the BusMatrix, allows the DMA to interact with AHB and APB peripherals. It can also perform memory-to-memory transfers and targets the same memory types as the DMA memory bus.
USB OTG HS DMA Bus
Specific to the USB OTG High-Speed DMA, this bus is used for loading and storing data to memory, targeting internal SRAMs, internal Flash, and external memories via FMC and QUADSPI.
BusMatrix
The BusMatrix serves as the control tower, managing interactions among all these buses. It uses a round-robin algorithm to decide which master gains access at a particular time. As illustrated in the figure above, the components at the top function as masters, while those on the right act as slaves. A circle at the intersection of the wires indicates a connection between a master and a slave.
AHB/APB Bridges
Two bridges, APB1 and APB2, connect the Advanced High-performance Bus (AHB) to the Advanced Peripheral Buses (APB), allowing for a flexible range of peripheral frequencies. After a device reset, you'll need to manually enable the clock for each peripheral you intend to use via specific RCC_AHBxENR or RCC_APBxENR registers.
Why Having Multiple Buses is Useful
The distinct buses allow data and instruction transfers to occur simultaneously or independently, which is a big plus for performance. This separation comes in handy for efficient pipeline execution and helps in reducing system bottlenecks.
2. Understanding AHB and APB Buses in STM32F446
In STM32F446's system architecture, the System Bus (S-Bus) serves as a bridge connecting the Cortex-M4 FPU core to the AHB1 and AHB2 buses. The AHB1 bus further connects to APB1 and APB2 buses through APB1 and APB2 bridges, providing a pathway to various peripherals.
Let's dive into the specifics of these AHB and APB buses:
Advanced High-performance Bus (AHB)
AHB is designed for high-performance, high-clock frequency system modules. It's the backbone for heavy data transfer and operation-intensive tasks.
AHB1: The Main Bus
Running at 180 MHz, AHB1 is the workhorse for the system. It handles a variety of high-speed operations and connects to high-speed GPIO ports (from A to H), DMA controllers, USB OTG High-Speed, and more.
AHB2: Specialized Functions
Also operating at 180 MHz, AHB2 is specialized for specific functionalities like DCMI (Digital Camera Interface) and USB OTG Full-Speed.
AHB3: Memory Control
AHB3 is your gateway to external memories, primarily handling the FMC (Flexible Memory Controller) control register and the QUADSPI (Quad Serial Peripheral Interface) register.
Advanced Peripheral Bus (APB)
While not as fast as AHB, APB is essential for connecting to peripheral devices, some of which don't require the high data transfer rates that AHB can provide.
APB1: The Slow Lane
Operating at a modest 45 MHz, APB1 is ideal for slower peripherals. These include I2C interfaces, SPI, USART communication, and various timers. Despite its slower speed, it’s crucial for many fundamental operations.
APB2: The Fast Lane
Clocking in at 90 MHz, APB2 is designed for peripherals that need faster data transfer but don't quite need the high speed of an AHB bus. This includes faster USART and SPI interfaces, as well as more advanced timers.
The architecture of these buses allows for a balanced distribution of tasks and data flow, giving you both the speed and flexibility to control a wide range of peripherals and processes. Understanding how to leverage each of these buses effectively can lead to more efficient and responsive system designs.